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Doesn't that mean hardware controls clock gating? Try using "force on" or "force off" and see what happens.

The PSE SPI f_input is 100MHz, but I don't know if it's the same for PCH SPI. Firmware might be able to change f_input for PCH SPI.

thanks i will try

Tried not effect,

Force on, no signal, Force Off works the same way(same frequency)

i tired with PSE SPI,, i am able to get the desired min to max Clock frequency, as per the give calculation,

not sure what is issue with PCH


Thanks
Ravi

I didn't see anything in the datasheets that would explain the PCH behavior. You might have to ask Intel directly.

OctocontrabasS

i have asked some time back yet to receive response from Intel


Thanks
Ravi

Hello Octocontrabass

I am trying to use PSE SPI1, RDC-614110, Intel ATom ELkhart lake

everything works fine

1) i check Status before putting anything in the Buffer (i.e waiting for TX FIFO to be 0, RX fifo to be 0 and device not busy)
2) CS asserts when the data is put in the FIFO
3) CS de asserts when FIFO is empty

occasionally every few thousand samples, what is happens is for example if the command is 8 byte wide , 6 bytes are transmitted under one sequence (i.e CS active-> data on the bus-> CS de-active) and 2 bytes are transmitted in separate sequence, this is creating lot of [problems(interrupts are disabled)

Thanks

You can't disable SMI.

Have you tried using DMA? SMI shouldn't interfere with DMA transfers.