Hello
sorry i should have include it
https://www.intel.com/content/www/us/en ... ume-1.htmlIntel Atom® x6000E Series, and Intel® Pentium® and Celeron® N and J Series Processors for IoT Applications
Datasheet, Volume 1
18.1.11 Interrupts
All interrupts are active high and their behavior is level interrupt. Controller interrupts
are enabled using the IER (Interrupt Enable Register) and read using the IIR (Interrupt
Identification Register)
yeah that was the issue when i configured as level triggered(either active or low), i get continuous interrupts uncontrolled (IIR/MSR reads no interrupts, and LSR indicates device busy in transmitting, when i check these registers while have come to ISR), i tired all the 4 combination Edge/level & Active-high/only, only thing that's working is edge triggered active low(when i enter the ISR, IIR reflects buffer empty INTR, and able to transmit the without any loss huge chunk of data),, i think level trigger is right way, i need to understand this behavior ASAP even though its working
"you need to acknowledge the interrupt in the UART before you send an EOI to the APIC"
here is what i do
when i first enter the ISR
Read IIR
Read MSR(no reason)
Read PCI status register
check if anything is pending in the buffer to be sent, if yes then put the next char in the THR
EOI IOAPIC
EOI APIC
IRET
Thanks for taking your time to answer my query
Ravi